1. Field of the Invention
This invention generally relates to a phase-locked loop (PLL) frequency synthesis system and, more particularly, to a frequency synthesis, low resolution, rational number frequency division system, such as might be used in a PLL.
2. Description of the Related Art
Conventional fractional-N frequency synthesizers use fractional number decimal values in their PLL architectures. Even synthesizers that are conventionally referred to as “rational” frequency synthesizers operate by converting a rational number, with an integer numerator and integer denominator, into resolvable or approximated fractional numbers. These frequency synthesizers do not perform well because of the inherent fractional spurs that are generated in response to the lack of resolution of the number of bits representing the divisor in the feedback path of the frequency synthesizer.
FIG. 1 is a schematic block diagram depicting an accumulator circuit capable of performing a division operation (prior art). As noted in “A Pipelined Noise Shaping Coder for Fractional-N Frequency Synthesis”, by Kozak et al., IEEE Trans. on Instrumentation and Measurement, Vol. 50, No. 5, October 2001, the depicted 4th order device can be used to determine a division ratio using an integer sequence.
The carry outs from the 4 accumulators are cascaded to accumulate the fractional number. The carry outs are combined to reduce quantization noise by adding their contributions are follows:
contribution 1=c1[n]:
contribution 2=c2[n]·c2[n−1];
contribution 3=c3[n]·2c3[n−1]+c3[n−2];
contribution 4=c4[n]−3c4[n−1]+3c4[n−2]−c4[n−3];
where n is equal to a current time, and (n−1) is the previous time, Cx[n] is equal to a current value, and Cx[n−1] is equal to a previous value.
FIG. 2 shows the contributions made by the accumulator depicted in FIG. 1 with respect to order (prior art). A fractional number or fraction is a number that expresses a ratio of a numerator divided by a denominator. Some fractional numbers are rational—meaning that the numerator and denominator are both integers. With an irrational number, either the numerator or denominator is not an integer (e.g., n). Some rational numbers cannot be resolved (e.g., 10/3), while other rational numbers may only be resolved using a large number of decimal (or bit) places. In these cases, or if the fractional number is irrational, a long-term mean of the integer sequence must be used as an approximation.
The above-mentioned resolution problems are addressed with the use of a flexible accumulator, as described in parent application Ser. No. 11/954,325. The flexible accumulator is capable of performing rational division, or fractional division if the fraction cannot be sufficiently resolved, or if the fraction is irrational. The determination of whether a fraction is a rational number may be trivial in a system that transmits at a single frequency, especially if the user is permitted to select a convenient reference clock frequency. However, modern communication systems are expected to work at a number of different synthesized frequencies using a single reference clock. Further, the systems must be easily reprogrammable for different synthesized frequencies, without changing the single reference clock frequency.
While it may be possible to resolve almost any fraction using rational division, practically, there are limits to the size of registers. That is, given the number of bit positions carried in a register, or series or registers, the numerator of some fractions may be resolved with more bits than there are bit positions. In that case, even a rational division system must truncate bits or make approximations, which result in PLL frequency jitter.
It would be advantageous if a means existed for determining a divisor in response to knowing the reference clock frequency and the desired synthesized frequency value. It would be advantageous if this means could determine if the divisor is a rational number. Further, it would be advantageous if the means could calculate the divisor in the form of a fraction that can be input into a flexible accumulator. Finally, it would be advantageous if a means existing for resolving rational division numerators with a minimum number of bits.